Free Essays on Gandhis Philosophy

â€Å"Life is not fair; deal with it† is spoken by parents and guardians within every society and creates a foundation to live by society’s rules and regulations, without following the values and morals of the individual. However, there are those who o not follows society's mold and struggle against everything for what they believe in. .Men like Henry David Thoreau, Martin Luther King Jr., and Mohandas Gandhi have led the way for to show everyone how to express there opinions in a non-violent manner to express their misgivings of society in hopes for change. All three stood up against society in their own civil disobedience paid the price for their actions and their viewpoint was heard and understood by other citizens within the society. Although each followed the same foundation for change, their struggles were for different reasons and acquired different results. Society has often denied individuals their rights, but there are always those who fight against it. Thoreau stood up for his beliefs by not paying taxes due to his objection of the taxation being used towards the Mexican War and enforcement of slavery laws. He felt that he had a right to object to the government using his money for things that he did not want to finance; he felt he had a right to protest in acts of civil disobedience. He went on to go to jail for his choice, choosing to remain non-violent. However he realized that his disobedience would not be recognized without publicity, and without publicity his point would not get across his actions would only be that of a criminal. He refused for anyone else to pay his taxes and would rather stay in jail than pay them, he showed that his actions were justified in his means; he displayed protest, which in turn represents his actions as civil disobedience. Since he wanted to make a change in the laws of the government, he was wil ling to stay in jail in protest in an attempt to make the government to reconsider the law, ... Free Essays on Gandhi's Philosophy Free Essays on Gandhi's Philosophy â€Å"Life is not fair; deal with it† is spoken by parents and guardians within every society and creates a foundation to live by society’s rules and regulations, without following the values and morals of the individual. However, there are those who o not follows society's mold and struggle against everything for what they believe in. .Men like Henry David Thoreau, Martin Luther King Jr., and Mohandas Gandhi have led the way for to show everyone how to express there opinions in a non-violent manner to express their misgivings of society in hopes for change. All three stood up against society in their own civil disobedience paid the price for their actions and their viewpoint was heard and understood by other citizens within the society. Although each followed the same foundation for change, their struggles were for different reasons and acquired different results. Society has often denied individuals their rights, but there are always those who fight against it. Thoreau stood up for his beliefs by not paying taxes due to his objection of the taxation being used towards the Mexican War and enforcement of slavery laws. He felt that he had a right to object to the government using his money for things that he did not want to finance; he felt he had a right to protest in acts of civil disobedience. He went on to go to jail for his choice, choosing to remain non-violent. However he realized that his disobedience would not be recognized without publicity, and without publicity his point would not get across his actions would only be that of a criminal. He refused for anyone else to pay his taxes and would rather stay in jail than pay them, he showed that his actions were justified in his means; he displayed protest, which in turn represents his actions as civil disobedience. Since he wanted to make a change in the laws of the government, he was wil ling to stay in jail in protest in an attempt to make the government to reconsider the law, ...

International Business Law Research Proposal Example | Topics and Well Written Essays - 1500 words

International Business Law - Research Proposal Example Some of the most common means under the present state of international business law are as follows: 1. Direct foreign sales - This is the present strategy of Hampstead, which is to sell directly to a foreign buyer (exportation). This option may not be applicable because our Company seems to have decided to set up a plant outside UK. 2. Licenses and franchises - This is typically accomplished by a licensing agreement. A license permits the licensee to exploit the subject matter of the license for a specified purpose and for a specified time. This option may not be applicable to our company the facts fails to indicate possibility. 3. Distributorships - In here, there is an agreement to market our company's products through the sales efforts of a foreign-based distributor. Under this arrangement, a distributor is free to develop the target market in any manner in which it sees fit; i.e., it is free to buy and sell for its own account, maintain inventories, and sell at prices it sets. In addition, foreign distributors sometimes receive added protection under local law. Another advantage is that a distributor may limit the supplier's (Hampstead, in this case) exposure to local tax and labor laws. The option seems to be one of our options with our plan in transporting the cars from UK to Mexico and just have a company based in Mexico to distribute our products. 4. Direct foreign investment - A domestic company may conduct international business through a subsidiary located in the foreign country. We know for a fact that a subsidiary corporation, typically, is one whose shares (typically, a majority of the voting shares, i.e., >50%) representing control of the corporation are owned by another corporation (the parent)." This option is also one that is currently considered by board. Hence, I like to point out that there is suggestion for having a wholly owned subsidiary to be controlled by our U.K. head office. Hence, this option may not allow it. However, we have the next option. 5. Branches - A branch is not a separate entity but is an extension of the domestic (e.g., U.S.) enterprise (e.g., corporation) in a host (i.e., foreign) country. It is also a practice that the enterprise might establish an operational spot in a host country, which requires direct investment in, for example, the following: 1) A research and experimental facility 2) A manufacturing plant for local sales and/or export 3) An operation that establishes a market and sales for its products and/or those of other enterprises It also mentioned the following relevant factors to operating in a host country using a branch: 1) A branch allows unqualified control as compared to operations by a subsidiary. 2) The form of a separate legal entity is not present to limit contractual or tort liability. 3) Risks of loss due to changes in host country governments are like as those associated with direct investment. This option seems to be applicable, if our Company will desire to have a 100-percent control of the decision-making. However, I have still a last option in the next. 6. A joint venture - Although a joint venture is usually thought of as a partnership, it may be engaged in by means of a corporation or other organizational form. With all due respect, may I be allowed to present to you the above options' Now if you will just allow me to

Racial inequality and political oppression of ethnic minorities leads Essay

Racial inequality and political oppression of ethnic minorities leads to typologies of criminal offenders. Discuss - Essay Example Racism as an ideology is illogical in principle and diverse in practice thus difficult to explain by a single definition. It permeates the family tree of societies and is reflected in all its attitudes, behavior, and institutions. The concept of racism may be conscious or subconscious and is expressed in actions or attitudes initiated by individuals, groups, or institutions that treat human beings unjustly because of their skin pigmentation. Racism is rooted in dysfunctional belief systems resulting from distorted perceptions formed over a period of time. We cannot ignore the significant role of the socio-cultural environment in shaping perceptual patterns. â€Å"Attitudes are a readiness or proclivity of an individual to respond in a certain way toward something† (Doobs, 1947: 138). People are inclined to respond on the basis of their own experience when it comes to social interactions and social biases such as racism. Therefore, people who have never experienced racism in a real sense have a tendency to downplay a condition of racism or discrimination. Minorities are more easily affected by racism as it is a more aggravated offense to them. Where you stand racially in a society determines your perspective on the issue. People of the majority in a social context have a propensity to feel that the world is, for the most part, a pretty fair place where people normally get what they deserve and deserve what they get. The virtuous are rewarded and evil doers are reprimanded, a conception of a just world resulting from our training as children. The inherent conclusion that can be drawn from that kind of reasoning is that those who are rewarded must be good, and those who suffer, if even from our own discrimination and prejudice, must deserve their fate (Rosado, 1998 ). If people do not see a situation as threatening to them they may conclude that it is not foreboding to others as well, often because they see the social system as

How can the strategic human resource business partner(SHRBP) add value Essay

How can the strategic human resource business partner(SHRBP) add value to the IT department - Essay Example Current paper aims to present the way in which the Strategic Human Resource Business Partner (SHRBP) can add value to the IT department and under which terms such task would be performed. Appropriate theories and models are used for justifying the role of SHRBP in the increase of value of IT department. The role of strategic human resource business partner (SHRBP) in the increase of value of IT department Strategic HR management can intervene in organizational activities at all levels of organizational hierarchy – reference is made to the organization as a unit, not just to the HR functions and sub-functions (Deb 2006). Of course, the role of HR within the organizations needs to be respected (Raj, 2007). In accordance with Morton (1999) when acting as a business partner, HR is expected to perform a series of roles: ‘strategic partner, change agent, administrative expert and employee champion’ (Morton 1999, in Armstrong, 2000, p.141). Moreover, Robinson et al. (2005) noted that HR can respond to the needs of its traditional role (deciding on the employees’ positions and tasks) as also to the needs of its strategic role (meaning the development of initiatives for the increase of organizational profits through the improvement of employee performance). As for the strategic HR management, this can intervene drastically in all organizational strategies identifying organizational failures and suggesting appropriate measures; in case that SHR manager acts as a business partner, then his ability to intervene in organizational strategies – at all organizational levels – is significantly increased. The involvement of SHRBP in the organization’s IT department would have a series of effects in the department’s structure, activities and performance. More specifically, the role of SHRBP in IT department would refer to the following activities: a) development and improvement of relationships of employees in order to improve communication and cooperation across the department; in this way, the performance of employees of the specific department would be also increased, b) improvement of information sharing; IT department is strongly depended on the management of informati

Digital Voltmeter Using An 8051 Microcontroller Computer Science Essay

Digital Voltmeter Using An 8051 Microcontroller Computer Science Essay A voltmeter finds its importance wherever voltage is to be measured. A  voltmeter  is an instrument used for measuring the  electrical potential  difference between two points in an electric circuit. Analog voltmeters move a pointer across a scale in proportion to the voltage of the circuit. General purpose analog voltmeters may have an accuracy of a few per cent of full scale, and are used with voltages from a fraction of a volt to several thousand volts. Digital voltmeters give a numerical display of voltage by use of analog to digital converter. Digital meters can be made with high accuracy, typically better than 1%. Specially calibrated test instruments have higher accuracies, with laboratory instruments capable of measuring to accuracies of a few parts per million. Meters using  amplifiers  can measure tiny voltages of micro-volts or less. Digital voltmeters (DVMs) are usually designed around a special type of  analog-to-digital converter  called an  integrating converter. Voltmeter accuracy is affected by many factors, including temperature and supply voltage variations. To ensure that a digital voltmeters reading is within the manufacturers specified tolerances, they should be periodically calibrated. Digital voltmeters necessarily have input amplifiers, and, like vacuum tube voltmeters, generally have a constant input resistance of 10 mega-ohms regardless of set measurement range. This project aims at building a Digital Voltmeter using an 8051 microcontroller. All the data accessed and processed by the microcontroller is the digital data. And thus, the usage of an analog-to-digital converter finds its necessity here. A standard analog-to-digital converter ADC0804 is used in the current project. The input voltage (which is the analog input) is restricted to be in the range of 0-15V. The processed data in the 8051 is used to drive a display output on a LCD display unit. The display is in the form of digits and is accurate to a value of one decimal. The input voltage is desired to be that of a DC voltage for steady observations of the voltage value on the LCD panel. Rather, if an AC input voltage is given at the input terminals, the output varies indefinitely as is the nature of AC voltage. Thus, the instantaneous value of the AC voltage is not steadily shown on the LCD panel. COMPONENTS Following is the entire set of the components used to build the Digital Voltmeter: Microcontroller, AT89S52 Analog-to-Digital Converter, ADC0804 161 LCD Oscillator circuit for the microcontroller 12MHz Crystal Capacitor 33pF Capacitors Voltage divider circuit/ Input terminals 200k, 100k Resistors 100nF Capacitor ADC Clock Circuit 10k Resistor 150pF Capacitor 100k Potentiometer (to adjust the back-light of the LCD) Description of the Components used Microcontroller, AT89S52 Æ’Â   The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density non-volatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional non-volatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. Pin configuration of the AT89S52 is as follows: 40-Lead PDIP VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification. P1.5 MOSI (used for In-System Programming) P1.6 MISO (used for In-System Programming) P1.7 SCK (used for In-System Programming) Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table. Alternate functions of port 3, P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Memory Organisation, Program Memory: If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory: The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. Interrupts: The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. ADC0804 Æ’Â   The ADC080X family are CMOS 8-Bit, successive approximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good common-mode-rejection and permits offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to a low encoding any smaller analog voltage span to the full 8 bits of resolution. The functional diagram of the ADC080X series of A/D converters operates on the successive approximation principle. Analog switches are closed sequentially by successive-approximation logic until the analog differential input voltage [VlN(+) VlN(-)] matches a voltage derived from a tapped resistor string across the reference voltage. The most significant bit is tested first and after 8 comparisons (64 clock cycles), an 8- bit binary code (1111 1111 = full scale) is transferred to an output latch. The normal operation proceeds as follows. On the high-to-low transition of the WR input, the internal SAR latches and the shift-register stages are reset, and the INTR output will be set high. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low to high transition. After the requisite number of clock pulses to complete the conversion, the INTR pin will make a high- to-low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion. A RD operation (with CS low) will clear the INTR line high again. The device may be operated in the free-running mode connecting INTR to the WR input with CS = 0. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion in process can be interrupted by issuing a second start command. Digital Operation The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting 1 level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a 1 to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this 1 to the Q output of DFF1. The AND gate, G1, combines this 1 output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a 1), the start F/F is reset and the 8-bit shift register then can have the 1 clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a 1 level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asynchronous or wide CS and WR signals. After the 1 is clocked through the 8-bit shift register (which completes the SAR ope ration) it appears as the input to DFF2. As soon as this 1 is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three-State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the three state output latches will be enabled to provide the 8-bit digital outputs. Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equivalent to the standard A/D Start and Output Enable control signals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an autozeroed comparator. The input capacitor is switched between VlN(+) and VlN(-), while two ratioed reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the current total value set by the successive approximation register. A correction is made to offset the comparison by 1/2 LSB. Analog Differential Voltage Inputs and Common- Mode Rejection This A/D gains considerable applications flexibility from the analog differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA 20mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VIN(+) and VlN(-) is 41/2 clock periods. There is maximum error voltage due to this slight time difference between the input voltage samples. The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input. Analog Input Current The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance to ground is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(-) input. These current transients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period. Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approximately 5uA. Therefore, bypass capacitors should not be used at the analog inputs or the VREF/2 pin for high resistance sources (>1kOhm.) If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate. Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors since the input currents settle out prior to the comparison time. If a low-pass filter is required in the system, use a low-value series resistor for a passive RC section or add an op amp RC active low-pass filter. For low-source-resistance applications, a 0.1uF bypass capacitor at the inputs will minimize EMI due to the series lead inductance of a long wire. A 100Ohm series resistor can be used to isolate this capacitor (both the R and C are placed outside the feedback loop) from the output of an op amp, if used. Stray Pickup The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize stray signal pickup (EMI). Both EMI and undesired digital-clock coupling to these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below 5kÃŽÂ ©. Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate this pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A/D (see Analog Input Current). This scale error depends on both a large source resistance and the use of an input bypass capacitor. This error can be compensated by a full scale adjustment of the A/D (see Full Scale Adjustment) with the source resistance and input bypass capacitor in place, and the desired conversion rate. Reference Voltage Span Adjust For maximum application flexibility, these A/Ds have been designed to accommodate a 5V, 2.5V or an adjusted voltage reference. This has been achieved in the design of the IC. Notice that the reference voltage for the IC is either 1/2 of the voltage which is applied to the V+ supply pin, or is equal to the voltage which is externally forced at the VREF/2 pin. This allows for a pseudo-ratiometric voltage reference using, for the V+ supply, a 5V reference voltage. Alternatively, a voltage less than 2.5V can be applied to the VREF/2 input. The internal gain to the VREF/2 input is 2 to allow this factor of 2 reduction in the reference voltage. Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VlN(MlN), is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the A/D VIN(-) input at this VlN(MlN) value. This utilizes the differential mode operation of the A/D. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN(-) input and applying a small magnitude positive voltage to the VIN(+) input. Zero error is the difference between the actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for VREF/2 = 2.500V). Full Scale Adjust The full scale adjustment can be made by applying a differential input voltage which is 11/2 LSB down from the desired analog full scale voltage range and then adjusting the magnitude of the VREF/2 input (pin 9) for a digital output code which is just changing from 1111 1110 to 1111 1111. When offsetting the zero and using a span-adjusted VREF/2 voltage, the full scale adjustment is made by inputting VMlN to the VIN(-) input of the A/D and applying a voltage to the VIN(+) input. Clocking Option The clock for the A/D can be derived from an external source such as the CPU clock or an external RC network can be added to provide self-clocking. The CLK IN (pin 4) makes use of a Schmitt trigger. Heavy capacitive or DC loading of the CLK R pin should be avoided as this will disturb normal converter operation. Loads less than 50pF, such as driving up to 7 A/D converter clock inputs from a single CLK R pin of 1 converter, are allowed. For larger clock line loading, a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the CLK R pin (do not use a standard TTL buffer). Restart During a Conversion If the A/D is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a new conversion is started. The output data latch is not updated if the conversion in progress is not completed. The data from the previous conversion remain in this latch. Continuous Conversions In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and INTR node should be momentarily forced to logic low following a power-up cycle to insure circuit operation. Interfacing the Microcontroller Interfacing the ADC0804 with 8051 Æ’Â   As shown in the typica circuit, ADC0804 can be interfaced with any microcontroller. A minimum of 11 pins are required to interface the ADC0804, eight for data pins and 3 for control pins. As shown in the typical circuit the chip select pin can be made low if you are not using the microcontroller port for any other  peripheral  (multiplexing). There is a  universal  rule to find out how to use an IC. All we need is the datasheet of the IC we are working with and a look at the  timing diagram  of the IC which shows how to send the data, which signal to assert and at what time  the signal  should be made high or low, etc. Timing Diagrams, Pin Description 1.  Ã‚  CS, Chip Select: This is an active low pin and used to activate the ADC0804. 2.  Ã‚  RD, Read: This is an input pin and active low. After converting the analog data, the ADC stores the result in an internal register. This pin is used to get the data out of the ADC 0804 chip. When CS=0 high to low pulse is given to this pin, the digital output is shown on the pins D0-D7. 3.  Ã‚  WR, Write: This is an input pin and active low. This is used to instruct the ADC to start the conversion process. If CS=0 and WR makes a low to high transition, the ADC starts the conversion process. 4.  Ã‚  CLK IN, Clock IN: This is an input pin connected to an external clock source. 5.  Ã‚  INTR, Interrupt: This is an active low output pin. This pin goes low when the conversion is over. 6.   Vin+ : Analog Input . 7.   Vin- : Analog Input. Connected to ground. 8.  Ã‚  AGND: Analog Ground. 9.  Ã‚  Vref/2: This pin is used to set the reference voltage. If this is not connected the default reference voltage is 5V. In some application it is required to reduce the step size. This can be done by using this pin. 10.   DGND: Digital Ground. 11-18. Output Data Bits (D7-D0). 19. CLKR: Clock Reset. 20. Vcc: Positive Supply The above timing diagrams are from ADC0804 datasheet. The first diagram shows how to start a conversion. Also you can see which signals are to be asserted and at what time to start a conversion. So looking into the timing diagram  we note down the steps or say the order in which signals are to be asserted to start a conversion of ADC. As we have decided to make Chip select pin as low so we need not to bother about the CS signal in the  timing diagram. Below steps are for starting an ADC conversion. I am also including CS signal to give you a clear picture. While programming we will not use this signal. Make chip select (CS) signal low. Make write (WR) signal low. Make chip select (CS) high. Wait for INTR pin to go low (means conversion ends). Once the conversion in ADC is done, the data is available in the output latch of the ADC. Looking at the second diagram, which shows the  timing diagram  of  how to read  the converted value from the output latch of the ADC, data of the new conversion is only available for reading after ADC0804 made INTR pin low or say when the conversion is over. Below are the steps to read output from the ADC0804. Make chip select (CS) pin low. Make read (RD) signal low. Read the data from port where ADC is connected. Make read (RD) signal high. Make chip select (CS) high. Interfacing the LCD with 8051 Æ’Â   Pin Information of LCD: Pin No Name Description 1 Vss Ground 2 Vdd +5V 3 Vee Contrast Adjustment -2V to -5V 4 RS Register Select 5 RW 1 -Read , 0- Write 6 E Enable Strobe 7 D0 Data Line 8 D1 Data Line 9 D2 Data Line 10 D3 Data Line 11 D4 Data Line 12 D5 Data Line 13 D6 Data Line 14 D7 Data Line 15 LED+ Backlit LED +V   Vdd (Optional signal) 16 LED- Backlit LED -V   Vss (Optional signal) Algorithm to send data to LCD: 1.Make R/W low 2.Make RS=0 ;if data byte is command RS=1 ;if data byte is data (ASCII value) 3.Place data byte on data register 4.Pulse E (HIGH to LOW) 5.Repeat the steps to send another data byte LCD Initialization: Proper working of LCD depend on the how the LCD is initialized. We have to send few command bytes to initialize the LCD. Simple steps to initialize the LCD Specify function set: Send  38H  for 8-bit, double line and 57 dot character format. Display On-Off control: Send  0FH  for display and blink cursor on. Entry mode set: Send  06H  for cursor in increment position and shift is invisible. Clear display: Send  01H  to clear display and return cursor to home position. Writing software: The LCD module is an intelligent component. We communicate to LCD module by sending commands from microcontroller. To write data to LCD module separate sequence is followed for 4 bit and 8 bit mode. Writing command for 8 Bit mode: Write 8 bit data on D0-D7 Generate strobe by taking EN from high to low Writing command for 4 Bit mode: Write 4 bit data (upper nibble) on D4-D7 Generate strobe by taking EN from high to low Write 4 bit data (lower nibble) on D4-D7 Generate strobe by taking EN from high to low LCD Commands:   Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Description NOP 0 0 0 0 0 0 0 0 0 0 No Operation Clear Display 0 0 0 0 0 0 0 0 0 1 Clear Display and Address counter = 0 Cursor Home 0 0 0 0 0 0 0 0 1 x Address counter = 0 Entry mode set 0 0 0 0 0 0 0 1 I/D S Set cursor direction(I/D) and auto display shift (S) Display Control 0 0 0 0 0 0 1 D C B Turn display (D) and cursor (C) ON/OFF. Set cursor blinking(B) Cursor/ Display shift 0 0 0 0 0 1 S R/L x x Shift display/cursor (S), specify direction (R/L) Function set 0 0 0 0 1 DL N F x x Set Interface data width (DL), number of display lines (N), character font (F) Set CGRAM Address 0 0 0 1 Set CGRAM address (D0-D5), CGRAM data is sent after this command Set DDRAM Address 0 0 1 Set DDRAM address (D0-D6), DDRAM data is sent after this command Busy Flag and Address 0 1 BF Read busy flag (BF) and address counter(D0-D6) Write Data 1 0 Write data (D0-D7) into DDRAM/CGRAM Read Data 1 1 Read data (D0-D7) from DDRAM/CGRAM Legends used in table:- I/D:  Ã‚  Ã‚  Ã‚  Ã‚  1- Increment, 0- Decrement S:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- Auto Display shift, 0 No display shift D:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- Display ON, 0 Display OFF C:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- Cursor ON, 0- Cursor OFF B:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- Cursor blinking ON, 0 Cursor blinking OFF S:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- Display Shift, 0 -Cursor move R/L:  Ã‚  Ã‚  Ã‚  1- Shift right, 0- Shift left DL:  Ã‚  Ã‚  Ã‚  Ã‚  1- 8 bit interface, 0- 4 bit interface N:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- 2 lines, 0- 1 line F:  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  1- 5X10 dots font, 0- 5X7 dots f

Islamic Societys Treatment of Women Essay -- Religion Islam Muslim

Islamic Society's Treatment of Women From the time of birth, a Muslim woman's place in Islamic society already has a shadow cast over it. Instead of the joyous cry that boys receive of "Allah Abkar"1 when they are born, a baby girl is welcomed into the world with a hushed Qurannic prayer. Although Islam venomously denies its role in the suppression of women, a survey of Islamic countries reveals that women are denied their humanity. The status of women in Islamic countries is undeniably inferior to men. Over the last twenty years, progress has been made in many countries which has helped elevate the roles which Muslim women play in their societies. Although progress has been made in certain countries, there still exist those Islamic countries where being born female guarantees a lack of rights, liberty, and happiness. This paper will explore the question, "What forces are limiting the Muslim woman's equivocal participation in Islamic society?" Islam's followers are approximated at 1.2 billion, which makes it a runner up only to Christianity that has about 2 million adherents. Women constitute about half of that population. However, it is important to note that this paper examines the treatment of women in the strongholds of the Islamic domain. These populations include the Arab countries of Saudi Arabi, Syria, Iran, Iraq, Pakistan, Afghanistan, Turkey, Jordan, Kuwait, Yemen, Israel, Oman, and Lebanon. Muslim women of the African countries of Sudan, Libya, Algeria, Egypt, Morocco, and Tunisia are also weighed in this analysis. In addition to these better known Islamic countries, the paper also observes the societal treatment of women in Turkmenistan, Uzbekistan, India, and Bangladesh. About 90... ...d rationalists of yesteryear who tried to import Greek ideas...Women have been, are, and will continue to be targets of intimidation and violence, whether from regimes in power or opposition movements that hark back to the past. It happened in Pakistan in the 1980s; it is still going on in Iran; and today at the beginning of the 1990s, it is happening in Algeria. Tomorrow the same thing can happen elsewhere...Today they constitute one of the most dynamic components of the developing civil society. Although up to the present they are still politically unorganized, they have succeeded in infiltrating one of the citadels which was long forbidden to them: formal education. Education, with high school and university diplomas, is women's new acquisition. Until now all women were taught to do, from housework to carpet weaving, was devalued and poorly paid.

Home Rehab Day at Tymco

During the rehab, the staff members from different units at Tymco became better acquainted. First, everyone in this activity shared ideas and took responsibility for what they were expert on. Second, they trusted each group to work on different things. At last, the case also provides evidence that people worked in Tymco who came from different units worked a lot with each other rather than worked with people from their own discipline.For example, Boudreau, the supervisor of technical documentation, worked with Benito from translation services and Jenkins from technical training, but not just worked with his own discipline workmates. Team spirit grows The home rehab day really gave a boost to team spirit. We can see that each member accepted assigned or self-appointed responsibility. They also discovered strengths and weakness. Only two days, they finished rehab the house. They worked well together. The ten participants painting the house together toward the end of the project showed that teamwork was developing.At the end of the day, they exchanged smiles, high fives and hugs [1], and received positive feedback from the family. Problems in the house rehab day At the end of the day, Ian, a staff from the technical manual group, commented that replacing shingles having no particular impact on becoming a better team player. Ian’s comment was valid on both sides: fixing shingles didn’t fix relationships, and also valid because fixing that shingle couldn’t consider you a team player.I agree with Ian’s comment because before we can have a better team player, it takes time to build up some bonds in order to get to work together. Maria and Cortez can’t really expect that a 2-days activity would change members’ perspective of working in a group. In my opinion, these kinds of activities should take place regularly maybe once a month. Also, the case mentioned that employees have actually never have lunch together, so maybe if they do that too, the relationship between them will be better.